cy62148e mobl ? 4-mbit (512k x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05442 rev. *f revised march 28, 2007 features ? very high speed: 45 ns ? voltage range: 4.5v?5.5v ? pin compatible with cy62148b ? ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a (industrial) ? ultra low active power ? typical active current: 2.0 ma @ f = 1 mhz ? easy memory expansion with ce , and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? available in pb-free 32-pin tsop ii and 32-pin soic [2] packages functional description [1] the cy62148e is a high performance cmos static ram organized as 512k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high). the eight input and output pins (io 0 through io 7 ) are placed in a high impedance state when: ? deselected (ce high) ? outputs are disabled (oe high) ? write operation is active (ce low and we low) to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight io pins (io 0 through io 7 ) is then written into the loca tion specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the io pins. product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62148ell tsop ii ind?l 4.5 5.0 5.5 45 2 2.5 15 20 1 7 cy62148ell soic ind?l/auto-a 4.5 5.0 5.5 55 2 2.5 15 20 1 7 notes 1. for best practice recommendations, refer to the cypr ess application note ?system design guidelines? at http://www.cypress.com . 2. soic package is available only in 55 ns speed bin. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 2 of 10 logic block diagram pin configuration [2, 4] a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 13 a 14 a 15 a 16 a 17 row decoder column decoder 512k x 8 array input buffer a 10 a 11 a 12 a 18 note 4. nc pins are not connected on the die. 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 32-pin soic/tsop ii pinout top view a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 v ss v cc a 18 we oe ce [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 3 of 10 maximum ratings exceeding maximum ratings may im pair the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65c to + 150c ambient temperature with power applied.......................... .................. ?55c to + 125c supply voltage to ground potential .................................?0.5v to 6.0v (v ccmax + 0.5v) dc voltage applied to outputs in high-z state [5, 6] ................?0.5v to 6.0v (v ccmax + 0.5v) dc input voltage [5, 6] ............ ?0.5v to 6.0v (v ccmax + 0.5v) output current into outputs (l ow)............................. 20 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch-up current ...... .............. .............. .............. ......>200ma operating range device range ambient temperature v cc [7] cy62148e ind?l/auto-a ?40c to +85c 4.5v to 5.5v electrical characteristics (over the operating range) parameter description test conditions 45 ns 55 ns [2] unit min typ [3] max min typ [3] max v oh output high voltage i oh = ?1 ma 2.4 2.4 v v ol output low voltage i ol = 2.1 ma 0.4 0.4 v v ih input high voltage v cc = 4.5v to 5.5v 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage v cc = 4.5v to 5.5v for tsopii package ?0.5 0.8 v for soic package ?0.5 0.6 [8] i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels 15 20 15 20 ma f = 1 mhz 2 2.5 2 2.5 i sb2 [9] automatic ce power down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = v cc(max) 17 17 a capacitance (for all packages) [10] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il(min) = ?2.0v for pulse durations less than 20 ns for i < 30 ma. 6. v ih(max) = v cc +0.75v for pulse durations less than 20 ns. 7. full device ac operation assumes a minimum of 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 8. under dc conditions the device meets a v il of 0.8v. however, in dynamic conditions input low voltage applied to the device must not be higher than 0.6v. this is applicable to soic package only. refer to an13470 for details. 9. only chip enable (ce ) must be high at cmos level to meet the i sb2 spec. other inputs can be left floating. 10. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 4 of 10 thermal resistance [10] parameter description test conditions soic package tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 c/w jc thermal resistance (junction to case) 10 13 c/w ac test loads and waveforms parameters 5.0v unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v data retention characteristics (over the operating range) parameter description conditions min typ [3] max unit v dr v cc for data retention 2 v i ccdr data retention current v cc = v dr , ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v ind?l/auto-a 1 7 a t cdr [10] chip deselect to data retention time 0 ns t r [11] operation recovery time t rc ns data retention waveform 3.0v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 v cc(min) v cc(min) t cdr v dr > 2.0v data retention mode t r v cc ce note 11. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 5 of 10 switching characteristics (over the operating range) [12] parameter description 45 ns 55 ns [2] unit min max min max read cycle t rc read cycle time 45 55 ns t aa address to data valid 45 55 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 45 55 ns t doe oe low to data valid 22 25 ns t lzoe oe low to low z [13] 55ns t hzoe oe high to high z [13, 14] 18 20 ns t lzce ce low to low z [13] 10 10 ns t hzce ce high to high z [13, 14] 18 20 ns t pu ce low to power up 00ns t pd ce high to power down 45 55 ns write cycle [15] t wc write cycle time 45 55 ns t sce ce low to write end 35 40 ns t aw address setup to write end 35 40 ns t ha address hold from write end 0 0 ns t sa address setup to write start 0 0 ns t pwe we pulse width 35 40 ns t sd data setup to write end 25 25 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [13, 14] 18 20 ns t lzwe we high to low-z [13] 10 10 ns notes 12. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less, timing ref erence levels of 1.5v, input pulse levels of 0 to 3v, and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 13. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 14. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 15. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that t erminates the write. [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 6 of 10 switching waveforms read cycle no. 1 (address transition controlled) [16, 17] read cycle no. 2 (oe controlled) [17, 18] write cycle no. 1 (we controlled, oe high during write) [19, 20] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data io oe note 21 notes: 16. device is continuously selected. oe , ce = v il . 17. we is high for read cycles. 18. address valid before or similar to ce transition low. 19. data io is high impedance if oe = v ih . 20. if ce goes high simultaneously with we high, the output remains in high impedance state. 21. during this period, the ios are in output state and input signals must not be applied. [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 7 of 10 write cycle no. 2 (ce controlled) [19, 20] write cycle no. 3 (we controlled, oe low) [20] truth table ce we oe io?s mode power h x x high z deselect/power down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data io we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data io note 21 [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 8 of 10 ordering information speed (ns) ordering code package diagram package type operating range 45 cy62148ell-45zsxi 51-85095 32-pin thin small outline package ii (pb-free) industrial 55 cy62148ell-55sxi 51-85081 32-pin small outlin e integrated circuit (pb-free) industrial 55 CY62148ELL-55SXA 51-85081 32-pin small outline integrated circuit (pb-free) automotive-a contact your local cypress sales representative for availability of these parts. package diagrams figure 1. 32-pin tsop ii, 51-85095 51-85095-** [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 9 of 10 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical cont rol or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support system s where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 2. 32-pin (450 mil) molded soic, 51-85081 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 0.546[13.868] 0.440[11.176] 0.101[2.565] 0.050[1.270] 0.014[0.355] 0.118[2.997] 0.004[0.102] 0.047[1.193] 0.006[0.152] 0.023[0.584] 0.793[20.142] 0.450[11.430] 0.566[14.376] 0.111[2.819] 0.817[20.751] bsc. 0.020[0.508] min. max. 0.012[0.304] 0.039[0.990] 0.063[1.600] seating plane 1 16 17 32 0.004[0.102] 51-85081-*b [+] feedback [+] feedback
cy62148e mobl ? document #: 38-05442 rev. *f page 10 of 10 document history page document title: cy62148e mobl ? , 4-mbit (512k x 8) static ram document number: 38-05442 rev. ecn no. issue date orig. of change description of change ** 201580 01/08/04 aju new data sheet *a 249276 see ecn syt changed from advance information to preliminary moved product portfolio to page 2 added rtsop ii and removed fbga package changed v cc stabilization time in footnote #7 from 100 s to 200 s changed i ccdr from 2.0 a to 2.5 a changed typo in data retention characteristics(t r ) from 100 s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin corrected typo in package name changed ordering information to include pb-free packages *b 414820 see ecn zsd changed from preliminary to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35ns speed bin removed ?l? version of cy62148e changed i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (max) value from 2 ma to 2.5 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f=f max removed i sb1 spec from the electrical characteristics table changed i sb2 typ values from 0.7 a to 1 a and max values from 2.5 a to 7 a modified footnote #4 to include current limit removed redundant footnote on dnu pins changed the ac testload capacitance from 100 pf to 30 pf on page #4 changed test load parameters r1, r2, r th and v th from 1838 ? , 994 ? , 645 ? and 1.75v to 1800 ? , 990 ? , 639 ? and 1.77v changed i ccdr from 2.5 a to 7 a added i ccdr typical value changed t lzoe from 3 ns to 5 ns changed t lzce and t lzwe from 6 ns to 10 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns changed t sd from 22 ns to 25 ns updated the ordering information table and replaced package name column with package diagram *c 464503 see ecn nxr included automotive range in product offering updated the ordering information *d 485639 see ecn vkn corrected the operating range to 4.5v - 5.5v on page# 3 *e 833080 see ecn vkn added footnote #8 added v il spec for soic package *f 890962 see ecn vkn added automotive-a part and its related information removed automotive-e part and its related information added footnote #2 related to soic package added footnote #9 related to i sb2 added ac values for 55 ns industrial-soic range updated ordering information table [+] feedback [+] feedback
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